A QPSK MODEM FOR 2.5 MBPS DATA RATE A Thesis Submitted in Partial Fulfilment of the Requirements for the Degree of MASTER OF TECHNOLOGY By HARINDRA RAO to the DEPARTMENT OF ELECTRICAL ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY, KANPUR DEOEMBER, 1931 S.. A 7«518 I 2 C APS 1982 iJn. i^£ affaationais mamoiij of mtj sCdst l^ot^s.%, ^J^x. Un.clxajs£t cJ^ao CERTIPIOITB Certified that this work on "A QRSK MODEM FOR 2.5 MBPS DATA RATE" has been carried out by Harindra Rao under my supervision and that this has not been submitted elsewhere for a degree. December , 1 981 ( VISHWANATH SIRHA ) Assistant Professor Electrical Engineering Department Indian Institute of Technology KMiUR ACKlTOWLEDaiMtSlTT I wish to express my heartfelt gratitude to Dr. V. Sinha for his guidance and encouragement throughout the course of this work. The suggestions I obtained during those sessions of discussion were very stimulating, I take this opportunity to thank M/s A. Jain and S, Manoharan, ACES Research Engineers, for their valuable suggestions and help throughout the course of this work. My special thanks are due to Mr. A.C. Joshi and Mr, D.D. Singh for their immense help. I am grateful to my friends - M/s S.P. Gupta, S.S, Singh, Rakesh Ohadha, P.C. Pandey , Dirish Rumar, and S. Maik for their valuable help and co-operation. I express my thanks to Mr. J.S. Rawat for skilful typing of this thesis. December ,1 981 Harindra Rao TABLE OE CONTENTS Page ■LIST OP PIGUBES ^ LIST OP TABLES ■vTlli ABSTRACT CHAPTER 1 INTRODUCTION - ^ CHAPTER 2 THEORETICAL ANALYSIS OP QPSK MODEM 6 2.1 Introduction ^ 2.2 Modulator Characterization 6 2.3 Demodulator Characterization 7 2.4 Performance of QPSK CHAPTER 3 HARDWARE DESIGN AND REALIZATION 20 3-1 Introduction 20 3.2 Design of Modulator ' 20 3.3 Design of Demodulator 29 5.4 Simulation of Channel 45 ,3-5 Discussion 46 CHAPTER 4 PERFORMANCE OP TflE MODEM 47 CHAPTER 5 CONCLUSION 52 REFERENCES 55 APPENDIX I APPENDIX II v± LIST OF FIGURES Fig. Ro. Title Page 1 .1 Correlation receiver for M-ary decision pr oLlem 3 2.1 Mechanization of a QFSK modulator 8 2.2 QPSK Signal 8 2.3 Mechanization of a QFSK- demodulator 10 2.4 4-phase Costas (I-Q) loop 14 2.5 Clock recovery rectifiers 16 3.1 . QPSK modulator 21 3.2 QPSK demodulator 22 3.3 Converter 24 3.4 Level shifter 26 3.5 10 MHz Fierce oscillator 26 3.6 Differential amplifier 28 3.7 Phase shifter 28 3.8 Biphase modulator 30 3.9 Substractor 30 o m Phase detector 33 3.1 1 loop filter 35 3.12 Voltage controlled crystal oscillator(VCXO) 38 3.13 Full wave rectifier 38 3.14 Differential amplifier 40 3.15 Clock filter 40 3.16 Phase-locked loop 42 3-1 7 C omparat or 42 3.18 Livid 3- by -two 42 3.19 Decision logic and processor 44 3.20 Simulation of the channel 45 4.1 Bit SHE vs. bit error rate 49 4.2 Evaluation of the system performance 50 vii LIST OF TABLES Table No. Details Page 2.1 Relationship between input phase and detected output 10 3- 1 Relationship between ambiguity and corresponding correction 33 4- 1 Probability of error for QPSK modem 48 ABlLiTRACT Efficient modem design for high speed digital commu- nication system has been drawint.^ considerable attention of researchers world-wide . The necessity arises because of exponential growth of data traffic. An attempt has been made in this direction by a study of modem. The theoretical studi'='S follow hardware design and fabrication of a prototype modem which can handle data rates upto 2.5 Mbps. The performance of the mod-m, when compared with theoretical rv suits, show a close r-fsemblance between the two; th-: per- formance criterion being the usual ( signal- to-nois ratio) needed per bit to achieve diff er.-nt bit error rates (BER).- An operating manual is appended. GHIPTER 1 INTRODUCTION The present day digital technology makes the digital communication systems more reliable at economically attractive complexity. The exponential growth of communication traffic continues to \place a premium on choice of communication freq- uencies and channel bandwidth. As a result, there exists a need to investigate data-transmission techniques xhat are high in communication efficiencies, i.e., low energy per bit to noise spectral density ratio for a particular bit-error rate, and that simultaneously offer the possibilities of bandwidth conservation. The ultimate objective is to introduce bandwid t'^ saving techniques that do not overdegrade or overconplicate tne system design problems of synchronization, data demodulation, and detection. Various detection techniques have been studied in Tj J • It is fonnd that in binary detection the antipodal signaling, e.g., biphase shift keying (EPBK), gives the best perfor- mance compared to other binary techniques; because the distance space between the two signals is maximum. However, phase coherency is required at the receiver for coherent detection of PSK signal, which further complicates the system hardware. To overcome this difficulty, differential phase shift keying 2 (DPSK) is used. It is found that at small error pro bahili ties, an increase of 1 dB in signal energy would result in DPSK performing as well as PSK [2]* The binary transmissi on/dete- ction problem is readily extended to the M-ary case by considering M knovm signals. ( i.e., s^(t),- i = 1,2, ...M) for transmission/detection- The mechanization of the optimum receiver can be realized with a bank of M multipliers and finite time integrators of the type shown in Pig. 1 .1 , with the local input to the multiplier now being s^(t). The performance of various signal sets have been studied [ 1 ,3,4] . An orthogonal coding scheme produces error- free transmission in the unconstrained bandwidth for additive ifkite Gaussian noise (AWGH) channel .»eyond a certain thre^old of bit energy to noise spectral density. However this requires a- complex receiver structure for detection and the time taken for decoding becomes unusually large. So block orthogonal signaling is not much useful for a practical system where the bandwidth is limited. The requirement of hi^ data rate per unit bandwidth led to the advent of M-ary phase shift keying (MPSK). Though this system provides a very good data rate per unit bandwidth (E/B) performance, the complexity to implement the system for large M becomes prohibitive due to phase coherency requirement at the receiver. As in the case of BPSE, here 3 Fig. 1 .-1 Correlation recaiver for M-ary decision prolleia 4 also the MPSK with differential detection have been tried but the probability of error performance degrades [ • Hence a compromise between the complexity and data rate per unit band- width (R/B) has to be struck for a practical implementation of the scheme. BPSK systems have become quite common in real life applications. Experimental 8 0 PSK system has been reported [ 7] . To achieve a high R/B ratio at low probability of error we have undertaken to design and fabricate a QPSK modem because of the hardware and time constraints. With QPSK, without altering the signaling bandwidth, information rate can be doubled compared to the BPSK case. But one has to pay for this in terms of increased transmitted signal power. In fact, to keep the probability of error constant, the signal power must be doubled in' the case of QI‘SK as compared to BPSK. In QP'3-E the signal set consists of two orthogonal signals and their negatives. Thus the QPSK represent) s bi-orthogonal signal set. In contrast with Fig. 1.1, we note that only M/2 cross-correlators (matched filters) are required in a system that transmit M bi-orthogonal signals; this being one of the important advantages of a bio- orthogonal signal set over an orthogonal signal set. Furthermore, for the same number of signals the effective bandwidth for a bi-orthogonal set is one half of the orthogonal set [ 5] « i Thus, we reiterate our objective, in the thesis, of going for a QPSK modem design .and fabrication. We have ; 5 chosen a data handling capability (of the modem) of 2.5 Mbps from the availability of hardware components. This can easily accomodate 32 multiplexed channels each of voice grade ( 4 KHz) 8- bit PGM. Theoretical analysis of QPSK signal is presented in Chapter 2. Basic problem in such a modem is the phase coherency of the carrier. Various methods to obtain the carrier and clock synchronization are discussed. The performance of QPSK for an ideal channel is given. We have chosen bit signal energy to noise spectral density ratio for achieving a certain bit - error rate (BER) as the parameters of performance. The complete hardware realization of the modem is discussed in Chapter 3. First of all, a detailed block diagram of the modem is given. The design and function of each block is described. The complete circuit diagram is obtained for modulator and demodulator. Since we are interested in testing the performance of the modem, a channel has been simulated for experimental purposes. In Chapter 4» the performance of the fabricated modem has been given. A comparison has been made between the theoretically available performance results and those obtained experimentally from the prototype modem. Finally, we conclude the thesis in Chapter 5 which also outlines the scope of further studies in this area. We append the thesis with system operating manual* CHAPTER 2 THEORETICAL ANALYSIS OE QPSK MODEM 2.1 INTRODUCTION Our objective in this chapter is to reiterate well knovm theoretical details of a QPSK system- The synchronization problem for the coherent detection of QPSK has been discussed. Expression for probability of error for a QPSK system under ideal conditions has also been given. 2.2 'MODULATOR CHARACTERIZATION Daring a transmission interval of T seconds the trans- mitted signal is assumed to be characterized by the polyphase signal s(t) = f sin [w^t + ] (2.1) k = 0,1 ,2,3 w = Carrier frequency in rad/sec. S = Signal power In the QPSK case, the transmitted signal in eqn. (2-l) can be expressed in the form s(t) = iTs [d^(t) sin w^t + d 2 (t) cos w^t] (2.2) Where d^ (t) and d 2 (t) are digital waveforms (values +1) whose transitions occur at T-second intervals. Thus, for quadriphase 7 signaling the above equation siiggests the modulator as depicted in Pig. 2*1 . The four possible output phases and their d^ d 2 digit combinations are shown, in Pig. 2.2. It will be noticed that the two digit combinations are arranged in a cyclic code so that adjacent codes are separated by 90°. Actually, in the QPSK, the input data stream (d) is converted into two parallel data streams (s^ d.| and d 2 ) in such a fashion that two consecutive bits of input data (d) are put in the two parallel data streams and also each bit of serial data appears only once in any of the two parallel data streams. Por example, if d = D. Do D’ D1 D” D” Then 12 12 12 «1 = “1 I'l 01’ and d2 = D 2 D^ DJ Each parallel data stream modulates (BPSK) the carrier. The carriers for the two channels are in phase-quadrature having the same frequency. The outputs of the two BPSK modulators are added to get the QPSK signal. Thus, in QPSK, each symbol corresponds to two bits of information. 2.3 DEMODULATOR CHARACTERIZATION If one assumes that the channel is a A¥GN (additive white Gaussian noise), the received signal can be character- ized as Biphase Mod ulator 9 y(t) = s(t) + n(t) ='f5s sin(w^t+ )+ii(t) (2.3) where n(t) is a sample function of the AWGN process with one sided spectral density of watt/Hz. Under the assumptions of equiprobahle equal energy transmitted signals; the optimum receiver (assuming perfect synchronization) is mechanized by two phase detectors followed by the decision logic and processor (Fig. 2.3) [10]. If synchronization (carrier and symbol) is to be obtained from the received signal then the carrier and symbol recovery circuitry must also be incorporated into the receiver. Generally the received signal y(t) is to be filtered by a bandpass filter ai(p), for out of band noise rejection which gives the resulting output x(t) in the form x(t) = s(t) + n^(t) (2.4) n^(t) = N^(t) cos w^t - Ng(t) sin w^t (2.5) where it has been assumed that , the two-sided bandwidth of the EPF, H^(p), is sufficiently wide to pass the signal and ni^(t) is a Gaussian noise with a narrow band expansion about the actual frequency of the input and is expressed by its inphase and qmdrature ccsaponents. Fig. 2.3 • mechanization of a WFSK jemodulator TlSLii; 2.1 Relationship between injut phase & detected output Input I'hase Transcnitted Binary code ^1 ^2 ^1 0° Detection ^2 90° Detec +45 1 1 +Ve +Ve -45 10 +Ve -Ve +135 01 -Ve +Ve -135 00 -Ve -Ve 11 The Table 2.1 shows the relationship between the input phases, their digital assignments, and the polarity of detected output without any error in the absence of noise. 2.3.1 Carrier Recovery Since perfect carrier (reference) recovery is essential for error free detection, the performance of the demodulator circuit depends primarily on quality of the recovery circuit for the reference signal. Since highly stable oscillators are available, it is possible to establish a pha.se reference in the receiver which will track the varying phase and help in detecting the digital phase modulated signals. The reconstru- ction of a carrier for a polyphase signal can be accomplished in many ways; however, if the modulation scheme is to be successfully implemented one must provide an efficient and accurate method for establishing reference coherence in the receiver. This statement implies that the receiver must be capable of tracking the carrier phase at all times. The simplest carrier synchronization systems that satisfy this requirement consists of the generalization of the suppress ed-carrier tracking loops presented and analyzed in [11]- [13] to M phases. The reconstruction of a carrier reference from a polyphase (MPSK) signal can be accomplished by Mth power loop (the generalized squaring loop), the ’ ' generaliz^jj Costas (I~Q) loop, modulation wipe off techniques employing decision directed methods, etc. [8,10] . shall not discuss the mathematical details of various synchronization techniques, as these are readily avaHgtiie in[ 10] , From a practical point of view, the M-pha.Q^ Costas loop suffers for large M in that the Equipment needed for j.mplementation becomes prohi- bitively Oompiez. Other practical considerations regarding ULS© one circuit over the other follow the comments made in the above references. One final point is that the probabili-^ density function for either M-phase tracking loop exhibits equally probable ambiguities in the interval (0,277 ) and hence practical implementation of these circuits in combin^^^Qj^ with a data demodulator would imply providing a means resolving these ambiguities, which becomes increasing;j_y for larger M. There are various methods of resolvij^ phase ambiguities in practical systems [14] . ior exampj_g^ employ differential encoding of the signals or search for a known synchronization pattern within the data stream. In any case, a certain amount of signal energy must be expended to accomplish ambiguity resolution. our case, M is equal to four which is not too large for ^ phase Costas loop. Since performance 15 of Costas loop under various impaiiments of received signal is better than generalized squaring loop, we have chosen to go for Costas loop for carrier recovery in our modem (Fig. 2.4). We discuss the resolution of phase ambiguity in Chapter 3. 2 . 3.2 Clock Recovery The clock is also needed at the demodulator for further processing so that one can recover the exact transmitted data. Transmitted signal does not contain discrete spectral component of the clock. No linear network can recover a reference that does not exist. The clock is recovered from envelope variation of the received signal or by the non-linear operation on the demodulated baseband waveforms [15]. In contrast to the limited number of carrier regenerators there are many possible clock-generator circuits. We discuss here the rectifiers, which essentially recover timing information from envelope variations that accompany bandwidth- limit ed signals. A rectifier can provide excellent performance on a band -limited signal; other circuits mi^t be more suitable for wide band signals with constant envelopes. Square law and absolute value (’’linear") rectifiers were investigated in depth. Practical rectifier circuits Fig. 2.4 4 Phase Costas (I-Q) Loop 15 probably have cteracteri sties that lie between the ideal square law and absolute value extremes. Rectifiers can be used at the IF output (in our case there is no RF so at the input of the demodulator) or at baseband (Fig. 2.5) • All IF rectifiers supply a regenerated clock that is independent of carrier phase. The absolute value rectifier provides a clock with less noise jitter than does its square law counterpart [ 1 5] . The clock filter is a sharply tuned filter. Amplitude phase and noise transients of typical filters were examined in detail. It is found that a single tuned filter will serve our purpose. A single tuned filter may allow certain cycle- skip events that are much rarer with a high order filter. Cycle skips are extremely destructive if they occur in the bit synchronizer. Hence, a phase-locked loop (PLL) has been employed at the output of clock filter. The PLii takes care of cycle- skips. The characteristic of the PLL is such that once locked it takes a long time to be unlocked. One thing should be clear that at the output of tuned filter, the recovered clock frequency will be half of the actual clock employed at transmitter. So with the help of the PLL the required clock frequency is synthesized. 2.5*5 Decision Logic and Processor The decision rule is such that, if demodulated signal q^(t) or q 2 ('*') is positive, it correspond to 1 (binary) and 16 F 0/P R6 c tii — C lock PIl fs C ompa- Phase Clock 7p ^ fier Filter ^ rat or ad just oTp” (a) IF Rectifier Fig. 2,5 Clock recovery rectifiers. 17 it is 0 for negative values of signal. Thus at the demo- dulator there are two parallel data streams and they have to be converted into an appropriate serial data stream. The conversion is in such a fashion that any two consecutive bits of a parallel data stream are not adjacent in the serial data stream and also one bit will appear only once in the serial data, for example, if Q] q;’ ^2 *^2 ^2 *^2 then q = Q2 Q] Q2 ^2 This serial data (q) will be the output of the modem. 2.4 PEriPORM/iNCB OF QPSK Early work on performance of digital communication systems employing polyphase signals was developed by Cahn [6,16,19] . Arthurs and lym [9] presented a geometric interpretation of three basic data transmission systems. The probability of error of MPEK for large M under ideal conditions has been given in [ 1 ]. PgCm) ^ erfc (fy sin ) ( 2 . 6 ) where Y is symbol SNR 18 The probability of error of (^SK under ideal conditions, (i.e.,' the channel is an AWGrN, there is no ISI and there is no delay distortion introduced by the channel), is given [3] Fg(4} = erfc ^ erfc^ (2.7) where P = symbol error rate t? = Bit SIR = V/log2M. Prom Eqn. (2.6) it is evident that for fixed information rate operation, the SIR per bit and hence signal power S must be increased as M /log^M to maintain the constant symbol error rate with increasing M. However, the required signaling bandwidth reduces as 1/log2M. If we have fixed signaling bandwidth operation, maintaining the same symbol error probability with increasing M requires that SIR per bit (y ^) be increased as M /log 2 M while the information rate increases as log 2 M, However, to compensate for the increased information 2 rate, the transmitted power S must be increased as M [ig . Thus it is clear that coherent QPSK provides the same error probability performance as biphase PSK (BPSK) and requires only the half the bandwidth. So there is 3 d'b improvement in bandwidth at the cost of 3 db degradation in transmitted power. The relationship between bit error rate and symbol error rate is given [ 3 ] • 19 Pg^CM) = (2.8) ■ where = Bit error rate (BBR) for MPSK Pg^(4) = ^[ erfc Ty^ - Jr erfc^ VyJ (2^) The theoretical (calculated) and experimental values of HER for the fabricated modem for different values of Bit SUE have been compared in Pig. 4.1. In an ideal case a bandwidth f_ is sufficient to send & signal by BPSK at a rate f„ bits per second without intersymbol interference (I SI). This allows for upper and lower side bands with widths . In QPSK, it is ideally possible to send a choice of one out of four phases in a time Interval equal to the reciprocal of bandwidth B. Each choice represent two ^ bits of information and hence the bit rate is 2B. So for QPSK the bandwidth B will be [ 17 ]• - 2 ( 2 . 10 ) CHAPTER 3 HARDWARE DESICR AHD REALIZATION 3*1 INTRODUCTION In this chapter, we discuss hardware desigja for the QPSK modem, A hardware design tries to achieve theoretieal values within certain tolerance limits* These are dictated because of component considerations, and availability of components etc. The complete system model of the modulator and the demodulator has been shown in Pigs. 3*1 and 3 *2 respective l;i The specifications for the job at hand are: MODULATOR: INPUT: DATA TO BE TRANSMITTED, WITH THE CLOCK SEPARATELY AVAILABLE (INPUT TTL COMPATIBLE) INPUT DATA RATE = CLOCK EREQ. = f^ = 2.5 MBPS OUTPUT ; MODULATED SINE WAVE CARRIER AT EREQ, 10 MHz DEMODULATOR; INPUT; RECEIVED SIGNAL POSSIBLY CORRUPTED W CHANNE' BANDWIDTH OE BPE= 2*53 MHz T DESIRED OUTPUT; DETECTED DATA (TTL COMPAJtIBLB) 3*2 DESIGN OF MODULATOR Input to the modulator is a serial binary data at 2,5 Mbps. This may, in a practical situation, come from a 3.1 QPSK Modulator SP UJ ll. WuO: 1 <^UJO I < i XUi : 0.0 23 multiplexer of 32 voice grade S-toit, PGM channels appended with suitable control protocols. The circuit clock filter followed by the phase-locked loop (PLl) has been designed for the 2,5 Mbps rate. The system will also work for lower rates tut thef liter and the PLL have to be suitably modified. The modulator takes this serial binaiy data as its input and produces QPSK signal with the subcarrier frequency of 10 MHz. The modulator block diagram given in Pig. 3*1 is self explana- tory, however we shall discuss individual blocks in detail from design considerations. 3.2,1 Converter The serial input data applied to the modulator is converted into two parallel data streams in a particular fashion as discussed in Section 2.2. Obviously, the data rate in either channel will be half of the input data rate. We assume that in the serial data, coming from the source, transitions occur at the leading edge of the clock. In the laboratory this is readily available from a data generator. Since the transition in both the parallel daannels, if any, must occur at the same instants, we shall delay the upper channel P by a bit with the help of a flip-flop. Thus, we achieve the perfect synchronization of the two channels. The complete circuit diagram of the converter is shown in Pig, 3*3( together with an input and corresponding output waveforms Select (a) Circuit Diagram (b) Input and Output Waveforms Fig. 3-3 Converter 25 (Eig. 5 . 3 ( 13 )) « The 2- line to 1-line data selector (used in converter) enables us to send a known data pattern to resolve the phase ambiguities of the recovered carrier, before starting the transmission of actual data. All the flip-flops must be cleared before starting the operation. The following is the state of operation of the converter, When CLR =1 d^ = d» d 2 = d« CLR =0 d2 = d^ where dj' and d” are known data streams (to resolve phase ambiguity) and d| and d^ correspond to serial data to be transmitted. 3.2.2 Level Shifter Since the biphase modulator requires the amplitude of the modulating signal around +.5V and -.5V corresponding to data 1 and 0 of th^ respectively , the level of the digital (TTL output) signal is shifted Iqy the circuit of Eig. 3-4. 3.2.3 Carrier Oscillator [ 20] We need a veiy stable oscillator for carrier generation. The 10 MHz sine wave carrier is obtained Iqy a Pierce crystal oscillator as shown in Eig. 3*5. Some typical performance characteristics of the oscillator are given below. a. Crystal : 10 MHz b. Output : ,9V peak-to-peak for = 430(^ c. Permissible load: 100£^ 00 27 The circuit will oscillate with any standard crystal but the particular oscillating frequency is obtained by suitable adjustment of C . 5.2.4 Diff ejrential /smplifier For carrier or modulated signal amplification/addition, the video differential amplifier LM733 has been used. It has differential input and differential output configuration. However, it can be used in any mode depending upon the requirement. The gain can be adjusted between 10 to 400. The input and output resistances are around 250Kf>- and 20ft respec- tively. The maximum output current is 10 mA. A typical differential amplifier is shown in Pig. 3.6. 3.2.5 Phase Shifter The phase shifter can be realized with the help of a high slew rate operational amplifier. But due to nonavaila- bility of the component, the configuration shown in Pig. 3.7 has been used. It consists of an RC section, an emitter follower, and an amplifier. The phase shift between input and phase output is adjusted to be 45°. To increase the/ shift, similar sections have been cascaded. The phase shift (© ) is given as © = - tan"^ wRC (3.1) where C = + Input capacitance of tb.e emitter follower. 29 3.2.6 Biphase Modulator The biphase modulation (BPSK) is achieved by using balanced modulator LM1496. The biphase modulator is chara- cterized as When Modulating signal = +ve; Modulated signal = Carrier withoui any phase differaace . Modulating signal = -ve; Modulated signal = Carrier with 180° phase difference The modulating signal amplitude is chosen to be +.5V because the modulator saturates at about +.15V. Thus the output is free from amplitude variations, whereas there are changes in phase. The circuit diagram of biphase modulator is given in Pig. 3.8, The differential output of the modulator is fed to a differential amplifier which provides the proper gain and also tries to nullify the carrier leakage. 3.2.7 Adder The addition of the two biphase channels (P and Q) is performed by using the differential amplifier, LM733, (Pig* 3.9) « The output of the adder is the required QPSK signal- 3.3 DESIGN OP DEMOBUIATOR The received signal is fed to the demodulator with the objective to get the transmitted binary data as its output. 31 The objective is met with the help of a decision logic and processor circuitry which detects the transmitted data. To achieve this, the received signal is to be demodulated. Carrier recovery and clock recovery circuits are needed for unambigaous demodulation- 3.3‘1 Carrier Recovery Circuit It hsis been concluded in Sec. 2.3.1 that for QE'SK the Costas loop is an optimum choice for carrier recovery. The / Costas loop exhibits three equally probable ambiguities in the interval (0,2tc ). In our case the ambiguities are 90°, 180° or 270°. It implies that the recovered carrier may have a phase difference of 90° or 180° or 270° instead of having zero phase difference as required. Thus, if recovered carrier has any phase difference from fixed reference, the detected data should be corrected accordingly. This basically means a constant phase difference is to be introduced at all levels. This is done in the converter of the demodiHator with the help of 4- line to l-line data selector. Table 3.1 shows the relationship between different ambigiities and corresponding corrections to be made in detected data. The loop consists of phase detectors, multipliers, loop filter, voltage controlled oscillator (VCO) and phase shifters. 3. 3*1.1 Phase Detector A phase detector consists of a multi 32 a low pass filter* The output of the phase detector is proportional to the cosine of phase difference between two input signals. The multiplier has been realized by IM 1496 whereas an RC section has been used for low pass filter* The differential output of the mltiplier is fed to an operational amplifier (CA3100) through the low pass filters , which increases the signal level. The slew rate of the Op-ihip. is moderate, so it also suppresses some undesired higher frequencies. The complete circuit diagram of the phase detector is shown in Fig* 3*10 . The following is the typical characteristic of the phase detector. Phase detector sensitivity = 1.66 V/rad, Cutoff frequency of IPF = 2.84 MHz Though, the 3 dB fiv-quency of the IPF is required to be only 1.25 MHz, wider bandwidth (2,84 MHz) of IPF gives less distorted output waveforms and simultaneously the attenuation of higher frequency (20 MHz) will not be much degraded, 3. 3. 1,2 Multiplier The only difference in the multiplier and phase detector (as discussed above) is that in multiplier there is no low pass, filter. The differential output of the multiplier LM1496 is directly connected to the differential input of differential amplifier GA 3100 without any RC section (IPF) in between. All other values of components used are the same as in the phase detector. 33 TABLE 3.1 Relationship between axabigaity and corresponding correction Phase of rec overed carrier with respe- ct to correct ref ere nee Transmitted dibit Detected dibit ^2 Correction to be made to get correct dibit ^1 ^2 State of select switcl for correctii A B 0° ^2 h ^2 . 0 0 90° ^1 Dp ^2 1 0 180° ^2 ^2 ^2 0 1 270° ^2 Dp 92 ^1 1 1 750 ri t) ■C' !^ t IK s-dY II 11 .+ 8 Y HP ki5- ^15 < -5" 3.9g ]— T ^ T o +1 5Y 5 ^ g 8 . 2K I -Ir / T? — 1'3 f2 T'T TO' ""g — 8" LM1 496 1 2 3 4 5 6 7 .. 1 -,,. I o] r 6 . 8 ! i' i.. .-I 560 ri^ •t'W'-y— I — VW" 150 ^ ^'6 . 8K ^ QQp: I -i.. .. 1R 100P T 8 7 6 5 CA3100 12^4 __.J h ^.2l tK i 1 I 0/P: 10K •1 5Y Pig. 3.10 Phase Detector 34 3.5-1-3 Loop Filter [ 3»21] Loop filter is low pass filter that is placed between the phase detector output and the VCO modulation input. Funda- mental loop characteristics such as capture range, loop bandwidth, capture time, and transient response are controlled' primarily by the loop filter. The study of the phase-locked loop response to various disturbances reveals that the perfor- mance of the first order loop is not particularly outstanding. It is consequently necessary, in many cases, to increase the order by inserting a loop filter in the loop. The most frequently used devices are discussed in [ 21] . Finally, the integrator, with phase lead correction network, the transfer function (K^) of which is given by Eqn. (3 •2) is chosen. The circuit diagram of the loop filter is shown in Fig. 3»11(a) 1 + T.s Ej, (3*2) where T^ = R 2 C Tg = R^C To make transient suppression independent of amplifier response, the network may be embedded within the input resistor and R^ (Fig. 3 . 11 (b)). Besides rounding off /inhibiting pulses, this network adds an additional pole to the loop and may cause further overshoot, if the cutoff frequency (w^) is too close to the natural frequency (Wj^) of loop. It is desirable to have w^ five to ten times w^^ to get rid of this (a) Loop Filter suppression. Fig^ 3*11 Loop Filter. 36 problem. With these considerations, our system has the following specification. Lock-up time =140 {i sec = 31K rad/sec. Damping ratio ^ = .8 Lock range = + 1 . 25 KHz around centre frequency (10 MHz) Capture range = + 1 .0 KHz aroxmd centre frequency (id MHz) «c = ® ’'n Hhere 3»3.1.4 Voltage Controlled Oscillator Since the carrier firequency is very stable at tbe receiver (in Costas loop), the required frequency variation in voltage controlled oscillator, which tracks the carrier, is very small. We have designed voltage controlled ciystal oscillator (VCXO) because of this small frequency variation. The centre frequency (when control voltage V^ is zero) is 10 MHz The frequency variation is not very linear because of non- linear behaviour of the varactor diode. The control voltage may vary between +14V to -14V. The VCXO frequency decreases when contit)! signal is positive and vice-versa. The complete circuit diagram is shown in Fig, 3.12, Some adjustment of C| is necessary to put the crystal at exact centre frequency, i.e., 37 10 MHz, The VCXO is followed by an emitter follower to avoid the loading. The output level of VCXO is observed to be around 1,0V peak- to- peak, 3.3- 2 Clock Eecoveiy The baseband rectifiers have been used for clock recovery. The detected signals of both channels P and Q (Pig, 3*2) are fed to the clock recovery circuit. The theoretical details have already been discussed in Sec, 2,3 -2, It is assumed that the data varies randomly, A long stream of 1s or Os are not allowed because clock recovery is not feasible with such long sequences of either a 0 or a 1 , Now we shall consider the realization of the complete clock recovery circuit, 3. 3- 2.1 Rectifier A full wave rectifier has been used (Pig, 3*13)- Since the signal frequency is high with small amplitude, the point contact diodes (0A81 ) have been used for rectification. Since, the input of the rectifier is bipolar signal, the frequency of output wiH be double of the input frequency. 3-3- 2.2 Differential Amplifier The output of rectifier is amplified by using a differaatial amplifier. The required Amplifier is realized by using an OP-A®, CA 5100, having a moderate slew rate. 39 Ihe configuration shown in fig. 3.14 le used. The gain of the amplifier is given by Gain = -r-fe 5 . 3 -2. 3 Adder The addition of two channels: is performed by -tbe OF- AM (CA 3100 ). bince one channel gets inverted, what we aceally need is a substracter instead of adder. Thus the same configuration as discussed above (Fig. 3.14) (with 'gain = 1) is used. 3. 3. 2. 4 Clock Filter The clock filter design is shown in Fig. 3.15. The f tank circuit is tuned to the frequency , i.e. 1 .2 5 FIHz. At this place, a class C tuned amplifier could also be used. The filter is followed by an emitter follower to avoid the loading. The value of C used differs from calculated value because of input capacitance of emitter follower. 3.3. 2. 5 Phase-Locked loop (ILL) The clock filter which has been used is a single tuned filter, bo to avoid the cycle skips a phase- locked loop (ILL) has been employed which tracks the input frequency- The f frequency of the output of the clock filter is, whereas actual clock frequency is fg. Bo with the help of -the PhL 41 and a divide -by- two circuit, the required frequency (2.5 Mz) is synthesized. The required characteristics of the Flh is th oV- t i ^*2K >:2.2K 1 f I/P -^I/P 2 4 — - 4VU — 5-&' -c +8V =p.022^/ j ‘ ^5.6K J: ^6 ,-,] — Pig. 3-16 i'hase~locked loop (PLL) 0+1 57 27 470 .OU't f r' - H f- -I 1/1 1 K ±- ■i> 0/1 (TTL compf'tible) 8 7 6 5 .<^A710 1 2 _1_ _A 9' #^20i ^ I -87 Pig. 3.17 Comparator I/P 0/P Pig. 3.18.- Divide-by-Two 43 flip-flop (SM 7474). The circuit diagram is siiown in fig. 3.18. The flip-flops are to he cleared before the operation starts. 3.3.3 Decision Logic and Processor firstly, the signals q^(t) and both the channels are made TTl compatible by the cornpa-rator. The comparator has the same configuration as discussed in Section 3.3. 2.6. If there is no error, q^ and q 2 -wrill correspond to d^ and d 2 respectively, here the inverse of the operation (as carried out at the modulator) has to be performed to receive the serial data. The theorvstical description is given in section 2.3.3'. The complete circuit diagram is shown in fig. 3-19 with input and output waveforms. The 4-line to 1-line data selector (SN 74153) has been used to resolve the ambiguity in Costas loop as discussed in Section 3.3.1. The relationship between phases and the state of select input is given in i'nble 3*1. hn emitter follower has been used to, avoid the loadirig which provides the demodulated output. 3.4 SIMULATION Of CHANNEL Since it was not possible to test the modem on an actual physical channel, an ideal channel has been simulated. Uaussian noise is added to the modulated signal. The signal corrupted by noise is passed through a band pass filter (HPf). 44 (b) Input and Output Waveforms Fig. 3.19 Decision logic and processor 45 35.25 6P 6P 35.25/^ H -■3'fiV— -1 h ^^151P 1 . 64 ^■tH 225F ^L~ 5 SO Adder i>jrf ormance . A typical secondary obj-^ctive is to achieve thio bandwidth efficiency at a minimum practical expenditure of average signal-to-noise ratio in an additive white (raussian noise channel. Though the M-ary PStl provides a very good h/B performance, it is one of the most complex systems for practical implementation. Is a compromise between the per- lormance s-nd th - complexity of the system, wi'bh system gives a good h/B perfoimance . Hence this study has been carried out. We have shown in Chapter 4» that the performance of the ff brie; ted lit’bk modem in an AWG-h channel is quite satisfactory . The subcarrier frequency is quite high so one has to be careful about the layout of the modem. The system requires very accurate and stable phase shift at various stages. In the fabrication process, because of the nonavailability of 53 high slew rate operational amplifiers we could not realize ti:ie phpse shifters with ease. Since the frequency is quite hi. h M smr. 11 stray capacitance can give a .good amount of error in th'^ phase. Though the phase shifters (used in modem) work well, tne use of operational amplifiers will certainly improve the performance and the components needed will be very much reduc--sd. The differential amplifier IM 733 has got a high gain and widc^ bandwidth, oo it was giving trouble because of salt oac i 11 ; ti ons . One must take care of its proper input and output terminations. In the phase detector, the offset mil is vei'y critical. The correct centre frequency of the voltage controlled crystal o., dilator is ob';ained by adding an inductanc. in series with the crystal. Though, we have tried our best tO; keep tho centre frequency of VOXO and carrier frequency exactly the sanr- , slight difference could not be completely eliminated resultini-, in a very small phase error in carrier r''*ference. The carrier recovery can also be obtained baseband analog or digital processing. In case of baseband digital processing, the carrier recovery circuit can be composed of a very smell number of components, have used a passive clock filter. An active filter (notch filter) would have further improved the performance of clock recovery circuit. A cost analysis of liie modem is given in Appendix I. 54 The modem works well at 2.5 ^'^bps. However, one would like to desi^'^n a modem at higher data rate. This could be achieved by using high subcarrier frequency and corresion- din_,ly appropriate components. Also the phase ambiguity of the recovered caiTier could be resolved by using suita.ble codin| 4 /d‘^ codin,-, schemes, xiere we have not considered the eiioct 01 intersymbol interference, delay distortion and ihr*tie 3itt-n-a. ihase jitters are very destructive for this typH of system. One can also, go for 80 ISiv for better H/B performance provided the components are available. RjiiFiiiiejjCES 1 . Vontrees , H.L. i'heory i art 1" '’Iie%e ction , Estimation and Modulation Wiley, Eew York , 19 68. 2. laub, H , and schilling, D.l., ; "Principles of Communi- cation systems", McGraw-xiill, Kogakusha , 1971. 3* lindsey , »/ .C . and Isimon, M.a.,: "'Telecommunication i^ystems Engineering", Prentice -Hall, lew Jersey, 1973. 4. Jozencraft, J .M. and Jacobs, I.M., ; "Principles of Communication Engineering", John Wiley & Eons, Eew fork, 1967* 5* Etein, o- and Jones, J.J.: "Modern C oinmunib.ati on Irinciplea", x4cGraw-iiill , Hew York, 1967* 6. Cahn, O.xt.: "Performance of Digital Phase-Modulation Communication systems", IEEE Trans* Comm, system, vol. US-7, pp. 3-6, iviay 1959* 7* dogge, C.R., Jr.: "Carrier and clock Recovery for 8PsK bynchronous Demodulation", lEEi^; Trans-, on Comm,,vol, JOM-26, No. 5, pp* 526-533, May 1978. 8. Yamashita, T., bakata, T. and Iguchi, K,: "bynchronous phase demodulators for hi.h speed quadrature 1 EK trans- mission system", iujitsu scientific and Technical J., vol* 11, No. 4, pp. 57-80, Deo, 1975* 9* Arthurs, E. and Dym, H*: "On the optimum detection of di .ital signals in the presence of white G-aussian noise", I'iWb, Trans. Comm, byst., vol* GS-o, pp * 336-372, Dec. 1962 . 10. Dindsey, W.C. and Simon, PI.R.; "Carrier synchronization and detection of polyphase signals", IEEE Trans, on Conam., vol, COM-20, No. 3, PP * 441-454, June 1972. 11, Dtndeey, W.C. and Didday, R.D.: "bubcarrier tracking methods and communication system design", IEee Trans. Comm, Tech, , vol. COM-I 6 , pp. 541-550, Aug. 1968 . 56 12. iJindsey , W.C, and cjimon, M.K.: "The performance of supp- resaed carrier tracking loops in the presence of frequency detuning", i: roc. liDSIi), vol, 5B, pp . 1315 —I 32 I, .•ept. 1970. 13 * iiindsey, ;/,G. and oimon, i'-a.K.: "hata-aided carrier trackin,.: loops", Ibr,.-; Tran= - Comm. Technol., vol. 00ri-.l9, pp. 157-169, April 1971. 14 . Ttiuji, Y.: "i'hase ambiguity resolution in a 4-phase lyh modulation system with forward-error-correcting convolu- tional codes", COmtiAT Technical Review, voIj. 6, Ro. 2, pp. 357-377, Pall 1976. 15 . Gardner, P.M.: "hapid synchronization: carrier and clock recovery for high-speed, di,i,ital communications", i'dcrowave system News, vol. 6, No. 1, pp. 57-63, P'^b. /march 1976. 16. Cahn, C.K.: "Comparison of coherent and phase-comparison detection of a four phase digital signal", Iroc. IR£1 (correep.), vol. 47, p. 1 662, dept. 1959* 17* Bennet, W-R. and lavey, J.R.: "lata Transmission", I'icGraw-Hill, New York, 1965. 1b » Tiwari, A.L.: "A comparative study of various digltal modulation techniques", M.Tech. Thesis, leptt . of E.B. X « X . X' . Ran pur , Aug. 1 9B1 . 19 . Cahn, C.R.: "Combined digital phase and amplitude modu- lation communication systems", IBat;;, Trans . Comm. Syst., vol. C;i-8, pp. 150 - 155 , dept, i 960 , 20. trerkinj, M.fi,; "Ciystal Oscillator Resign and Tempera- ture Compensation", VNR^ New Yoris, 1978. 21. Blanchard, A,: "Phase-locked Loop", John ¥iley & dons. New York , 1 976. APPENDIX I CARD DESCRIPTION The modem consists of three cards (PGB) Card No. Details No. of ICs used 1 Modulator 12 2 Demodulator I 20 {from IC1 to IC20) 3 Demodulator II 12 (from IG21 to IC32) The pin connections of the cards are shown in Pig. 1.1. POWER SUPPLY’ The modem requires +5VDC , +8VDC and +1 5VDC voltages for its operation. We provide the required d.c. voltages from external sources. TIME LAG The time lag between input and output of the modem is 1.54 Nsec. COST The costs of the components used in modulator and demodulator are Rs. 650/- and Rs. 2250/- respectively* Keeping a rule of thumb for the production cost to be approximately 5 times the component cost, the cost of the modem would come approximately to Rs. 15000/-. 1-2 Card No. 1 1 NO 2 Modulated 0/P 3 -8VDC 4 d" 2 5 CLR 6 Clock I/P 7 1 +5VDC 1 8 r : Data I/P 9 d;' 10 +6VDC 11 +1 5VDC 12 GND Card No. 2 1 ' +1 5VDC 2 -1 5VDC 3 Demodulated 0/P 2 4 Demodulated 0/P 1 5 NC 6 NG 7 1 NC 8 Modulated I/P 9 -SVDC 10 +8VDC 1 1 1 NC 1 12 ; GND Card No. 3 1 GND 2- +8VDC 3 +1 5VDC 4 -157DC 5 Demodulated I /PI 6 Demodulated l/P2 7 -8VDC 8 +5VD0 n Data 9 0/P 10 SELECT B 1 1 SELECT 1 1 2 CLR *NC => Not connected Fig. 1.1 Pin Connections of the Cards. APPJ5NDIX II BIBLIOGRAIHT 1. Costas J.P.: "bynchronous Communications'* Proc. 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Linkovskii G.B.: "Approximate determination of the probability of correct detection in the case of optimum reception of a signal with unknown phase", Soviet' Radio Lng^., vol. 8, ho. 4, pp . 345-349, Jul.-Aug. 1965* 9 . Bellow P.A.: "Bounds on the error probability of P'SK and PSK receivers due to non-Gaussian noise in fading channels", IBLn Trans. Inform. Theory, vol. IT-12, No. 3, pp. 315 - 326 , July 1966. 10. Bussgang J.J. and Teiter M.: "Phase shift keying with a transmitted, reference", IhiiB Trans. Comm,. Technol., vol. COM-14, No. 1, pp . 14-21, Feb. 1966'. II -2 11. Iwasaki S., ilawafune i'., iachikawa K., Ito S. and Yokoyama S.; ''i'our phase modulator and demodulator for microwave comniunicaxion system using pulse code modulation'*, J. Inst. Sleet. Comm. Sngrs. Japan, vol. 49, 1 ^ 0 . 11, pp. 2125-2131, Nov. 1966. 12. Lindsey W.C.: "I’hase-shif t-keyed signal detection with noisy reference signals", ISSS I'rans . Aerospace Slectronic byst . (UbA) , vol. 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Cripps I.N. and Macdonald C.ri.: "Practical realization of 250/500 i-'ibps PSK modulators and demodulators ", Conference on Trunk Telecomm, by Guided waves, London, 29 aept. - 2 Oct. 1970 (London, ’England: lEB 1970), pp. 351-354. 38. Cripps P.K.-: "A theoretical appraisal of high speed PBIC modulation techniques", Conference on Trunk Telecomm, ty Guided waves, London, 29 bept.-2 Oct. 1970 (London, England: III 1970), pp. 346-350. 39. Lindsey 9.C. and Simon M.K.: "The performance of suppressed carrier tracking loops in the presence of frequency detuning," Proc. IEEl , vol. 58, pp . 1315-1321, bept. 1970. 40. Rosenbaum A.b.: "Error performance of multiphase NPok with noise and interference", lEbE Trans. Comm, i'echnol., vol« COi'L-18, No. 6, pp. 821-824, Dec. 1970. . 41 . bunagaw ii., bugai T. and ohimizu I.: "Digital four-phase modulation system for wide hand data transmission", Rev, Elec. Comm. Lab. (Japan), vol. 1b, No. 5-6, pp.. 325-344, May 1970. 42. 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Klapper J., Frankie J.P.: "Ihsse-locked and frequency- feedback systems", Academic Press, lew York, 1972. 49. Lindsey ¥.C. and bimon M.£.: "Carrier synchronization and detection of polyphase signals", IB iL i'rans. Comm., vol. COM-20, lo. 3, pp* 441-454, June, 1972. 50. Lindsey i.C., bimon M.K.: "On the detection of differen- tially encoded polyphase signals", iBjjiD Prans . Comm., vol. COM-20, No. 6, pp,. 1121-1128, Dec. 1972. 51. Yamamoto H., Hirade n., Watanabe I.; "Carrier synchro-' nizer for coherent detection of high speed four— phase— shift-keyed signals", IBJL i'rans. Comm. Pechnol. , vol. GOM-20, No. 4, Pp • 803-B07, Aug. ^1972. 52. Chau jj.K.; "iirror rate of a 4-phase coherent ItHL satellite channel with non-Gaussian interference", IBi^E Int. Conf. on Comm., vol. I, beattls, Wash,, DbA, 11-13 June, 1973, p. 8/10-24. 53. Hata M., Iwano 1., Ono b., Ohta, I'., Masuda Y., : "20 GHz high bit rate transmission equipment with a new demo- dulator" , IiiiBB Int. Conf. on Comm., vol. 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